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<p>连上,大家好,以下几个职位是接上面的,因上面写不下,谢谢各位的关注</p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><b style="mso-bidi-font-weight: normal;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">5.System Engineer-Shanghai <p></p></font></span></b></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">QUALIFICATION (DETAIL): <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">Education: <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???BS Electrical or Computer Engineering, MS preferred <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">Experience: <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Three or more years of related industrial experience desired <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Good computer HW/SW systems knowledge. Programming skills in C/C++, Perl, and assemble languages is a plus. <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Knowledge of PCI bus and/or other digital systems interface standards <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Enjoys hands on lab work using test/measurement equipments (logic analyzer, oscilloscope, spectrum analyzer, in-circuit emulator) <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Experience with board level SOC designs with MIPS, ARM or equivalent embedded processors <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Strong trouble shooting and analytical skills <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Verilog RTL and FPGA skills a plus <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Knowledge of Wireless LAN protocols or cellular wireless communication protocols a plus <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Highly motivated, fast learner, team player with good communication skills <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">DESCRIPTION OF FUNCTION & RESPONSIBILITY: <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Design hardware platform for validating chips and system solutions <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Develop hardware validation tests, scripts and tools <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Verify and trouble shoot board level reference designs <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Debug customer functional and performance issues <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Digital, analog, and RF board level debug; hardware and software systems integration and debug <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Systems will include Bluetooth Headset, Bluetooth USB, and embedded CPU, memory subsystems<p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><p><font face="Times New Roman">
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</font></p></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><b style="mso-bidi-font-weight: normal;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">6.Test Development Engineer-shanghai <p></p></font></span></b></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">Education: <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???BS Electrical or Computer Engineering, MS preferred <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">Experience: <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???3 years of related ATE software development & debugging experience desired <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Experience on Teradyne Catalyst/iFLEX/Ultra-Flex or Agilent 83K/93K preferred <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Good communication skills in English <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">DESCRIPTION OF FUNCTION & RESPONSIBILITY: <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">Job Overview: <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">The ATE Test Engineer will develop ATE test software/hardware for Atheros IC products. A strong understanding of the ATE test system structure, IC test program structure, DC/AC/RF test will be needed. An ideal candidate for this position is someone who enjoys the challenge of developing complicated IC test solutions, and is a fast learner with strong commitment to results. <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">Duties/Responsibilities: <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Design test hardware/software for Atheros SOC chips <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Debug bugs in the test programs <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">Skills/Experience: <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Good ATE systems knowledge <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Programming skills in C/VB languages <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Knowledge of Digital/Mixed-Signal/RF IC testing, <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Enjoys hands on lab work using test/measurement equipments (oscilloscope, spectrum analyzer) <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Experience with Loadboard Design <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Strong trouble shooting and analytical skills <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Perl Script Language skill & Pattern Conversion skill a plus <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???RF experience a plus <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Highly motivated, fast learner, team player with good communication skills <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???US visa owner as a plus<p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><p><font face="Times New Roman">
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</font></p></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><b style="mso-bidi-font-weight: normal;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">7.Product Engineer-shanghai <p></p></font></span></b></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">QUALIFICATION (DETAIL): <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">Education: <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???BS Electrical or Computer or Communication Engineering, MS preferred <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">Experience: <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???3+ year in IC product engineering, or design engineering, or test engineering, or reliability engineering <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">DESCRIPTION OF FUNCTION & RESPONSIBILITY: <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">The Product Engineer will be responsible for technical support for Atheros IC products. A strong understanding of the wireless product concept, IC testing, IC Qualification, Wafer processing will be needed. An ideal product engineer should also be a highly motivated, fast learner, team player with good communication skills <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???New product correlation & release into production <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???IC production yield enhancement supporting, supporting WS and FT <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Device characterization on System & ATE <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Supporting IC product qualification <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Project management experience <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Knowledge on wireless communication protocol is a plus <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???RF experience as a plus <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???US visa owner as a plus <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">SPECIAL REQUIREMENTS: <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???3 + years of related experience in Product Engineering <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Good communication skills in English <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Knowledge in IC flows, wafer processing, testing, and qualification <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Knowledge in communication IC products<p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><p><font face="Times New Roman">
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</font></p></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><b style="mso-bidi-font-weight: normal;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">8.Sr. DSP Engineer <p></p></font></span></b></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">QUALIFICATION (DETAIL): <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???MSEE.or Ph.D. With 5+ years of experience in developing, implementing, and debugging high-performance communications and DSP ASIC products. <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Strong academic background of digital communication theory with proficient Matlab/C programming and simulation skills. <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Extensive verilog RTL experience including design, verification, synthesis, and debugging. <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Proficiency of Xilinx FPGA prototyping. <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Solid hands-on experience of using different lab equipment such as oscilloscopes, logic analyzer, signal generator, spectrum analyzer, etc. <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Fluency in English reading and writing. <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???IEEE 802.3 or previous Ethernet product development experience is a plus. <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">DESCRIPTION OF FUNCTION & RESPONSIBILITY: <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">The candidate will join a team of algorithm design and FPGA prototyping involved in the development of advanced digital signal processing algorithm for the physical layer of high speed wired data communication IC. <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Design and develop PAM/QAM single/Multi-carrier transceivers, multi-input adaptive equalizers/echo cancellers, multi-dimentional trellis encoder/decoder, timing recovery, digital filters, interface with analog blocks and MAC/switch blocks. <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Create bit-exact Matlab/C system model and perform simulation. <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Design and simulate verilog RTL code using synopsys and cadence EDA tools. <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Prototype, debug and verify RTL code on Xilinx multi-FPGA platform. <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Perform coding, synthesis, timing closure, placement and route on FPGA.<p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><p><font face="Times New Roman">
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</font></p></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><b style="mso-bidi-font-weight: normal;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">9.Software Engineer </font></span></b><b style="mso-bidi-font-weight: normal;"><span style="FONT-SIZE: 12pt; FONT-FAMILY: 宋体; mso-ascii-font-family: "Times New Roman"; mso-hansi-font-family: "Times New Roman";">(</span></b><b style="mso-bidi-font-weight: normal;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">Network Device Driver Software</font></span></b><b style="mso-bidi-font-weight: normal;"><span style="FONT-SIZE: 12pt; FONT-FAMILY: 宋体; mso-ascii-font-family: "Times New Roman"; mso-hansi-font-family: "Times New Roman";">)</span></b><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">
<p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">QUALIFICATION (DETAIL): <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">Education: <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Typically requires MSEE/CS combined with 3+ years of related experience, or BSEE/CS combined with 5+ yrs related experience. <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">Experience: <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Hand-on C and C++ in Linux or Unix environment. <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???3+ years industrial experience in multi-processor, multi-process, and multi-thread programming. Familiar with IPC and synchronization. <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Familiar with make tools, shell language, CVS/Perforace and GDB. Familiar with KGDB is a plus. <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Familiar with device driver and register level programming. Experienced with Linux kernel and Linux device driver model is very desirable. <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Must be speaking fluent English & a team player. <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Must be comfortable with large scale team based SW development and frequent inter-group/company communication. <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Experienced with ASIC verification or BIOS development is a plus. <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">???Hi-end networking nic/switch/router SW development experience is a plus. <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">DESCRIPTION OF FUNCTION & RESPONSIBILITY: <p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">Register level device driver implementation for high speed complex networking components; Linux kernel related development.<p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><p><font face="Times New Roman">
</font></p></span></p><p class="Default" style="MARGIN: 0cm 0cm 0pt; LINE-HEIGHT: 150%;"><b><span lang="EN-US"><font face="Times New Roman">10.Field Application Engineer- Shenzhen </font></span></b></p><p class="Default" style="MARGIN: 0cm 0cm 0pt; LINE-HEIGHT: 150%;"><b><span lang="EN-US"><font face="Times New Roman">QUALIFICATION (DETAIL): </font></span></b></p><p class="Default" style="MARGIN: 0cm 0cm 0pt; LINE-HEIGHT: 150%;"><span lang="EN-US"><font face="Times New Roman">???Communication, Computer Science, and EE bachelor or above </font></span></p><p class="Default" style="MARGIN: 0cm 0cm 0pt; LINE-HEIGHT: 150%;"><span lang="EN-US"><font face="Times New Roman">???At least 3 years working experience </font></span></p><p class="Default" style="MARGIN: 0cm 0cm 0pt; LINE-HEIGHT: 150%;"><span lang="EN-US"><font face="Times New Roman">???Networking hardware design/testing experience must </font></span></p><p class="Default" style="MARGIN: 0cm 0cm 0pt; LINE-HEIGHT: 150%;"><span lang="EN-US"><font face="Times New Roman">???WLAN design or testing experience preferred </font></span></p><p class="Default" style="MARGIN: 0cm 0cm 0pt; LINE-HEIGHT: 150%;"><span lang="EN-US"><font face="Times New Roman">???Good at reading/writing English </font></span></p><p class="Default" style="MARGIN: 0cm 0cm 0pt; LINE-HEIGHT: 150%;"><span lang="EN-US"><font face="Times New Roman">???Good team player </font></span></p><p class="Default" style="MARGIN: 0cm 0cm 0pt; LINE-HEIGHT: 150%;"><b><span lang="EN-US"><font face="Times New Roman">DESCRIPTION OF FUNCTION & RESPONSIBILITY: </font></span></b></p><p class="Default" style="MARGIN: 0cm 0cm 0pt; LINE-HEIGHT: 150%;"><span lang="EN-US"><font face="Times New Roman">???Provide technical support to customer, including FA, RMA, etc. </font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt; LINE-HEIGHT: 150%;"><span lang="EN-US" style="FONT-SIZE: 12pt; LINE-HEIGHT: 150%;"><font face="Times New Roman">???Conduct training to customer<p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><p><font face="Times New Roman">
</font></p></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt;"><p><font face="Times New Roman">
</font></p></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><b><span lang="EN-US" style="FONT-SIZE: 12pt;"><font face="Times New Roman">11.RF and Analog Layout/Mask Designer<p></p></font></span></b></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt; COLOR: black;"><font face="Times New Roman">Three or more years of experience in analog and RF layout/mask design. <br/><span style="mso-spacerun: yes;">
</span>Must have experience Cadence Virtuoso layout editor<br/>. Must have experience with LVS/DRC. <br/>. BSEE required.<p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt; COLOR: black;"><font face="Times New Roman">Job Description<br/>Work in <city wst="on"><place wst="on">Shanghai</place></city> on Analog Mask Layout <br/>Support RF and Analog IC layout in Cadence Virtuoso environment.<p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt; COLOR: black;"><p><font face="Times New Roman">
</font></p></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt;"><span lang="EN-US" style="FONT-SIZE: 12pt; COLOR: black;"><p><font face="Times New Roman">
</font></p></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt; LINE-HEIGHT: 150%;"><font face="Times New Roman"><b><span lang="EN-US" style="FONT-SIZE: 12pt; LINE-HEIGHT: 150%;">12.RF Applications Engineer</span></b><b style="mso-bidi-font-weight: normal;"><span lang="EN-US" style="FONT-SIZE: 12pt; LINE-HEIGHT: 150%;"><p></p></span></b></font></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt; LINE-HEIGHT: 150%;"><span lang="EN-US" style="FONT-SIZE: 12pt; COLOR: black; LINE-HEIGHT: 150%;"><font face="Times New Roman">Minimum Requirements<br/>Five or more years experience in design cellular phone reference designs<br/>for GSM, EDGE, TD-SCDMA or WCDMA.<br/>Expertise and understanding of system including RF and BB<br/>Experience in firmware development and bring-up of cellular phone modules<br/>Experience in bringing cellular phone designs to production<br/>Experience in FTA testing environment<br/>Experience in DigRF requirements of cellular phones<br/>Detailed knowledge of 3GPP specifications<br/>Knowledge of 3GPP requirements and module design<br/>Good communications skills<br/>BSEE required, MSEE preferred.<p></p></font></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt; LINE-HEIGHT: 150%;"><span lang="EN-US" style="FONT-SIZE: 12pt; COLOR: black; LINE-HEIGHT: 150%;"><p><font face="Times New Roman">
</font></p></span></p><p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt; LINE-HEIGHT: 150%;"><span lang="EN-US" style="FONT-SIZE: 12pt; COLOR: black; LINE-HEIGHT: 150%;"><font face="Times New Roman"> Job Description<br/>Design cellular phone reference designs for GSM/GPRS/EDGE , TD-SCDMA and<br/>WCDMA<br/>Responsible for full characterization and FTA of cellular phone module<br/>Responsible for RF performance tuning and debugging<br/>Responsible for customer support<br/>Responsible for management of vendors</font></span><span lang="EN-US" style="FONT-SIZE: 12pt; LINE-HEIGHT: 150%;"><p></p></span></p><p></p> |
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